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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . h i gh - p e r f o r m a n c e s t e p - d o w n p w m c o n t ro l l e r w i t h p f m f e a t u r e s operates from an input battery voltage range of +3v to +25v 0.6% 0.5v reference - over line, load regulation, and operating temp. drive dual low cost n-channel mosfe ts - adaptive shoot-through protection power-on-reset monitoring on vcc pin pfm mode for increasing light load efficiency constant-on-time control scheme - switching frequency compensation for pwm operation 300khz constant switching frequency integrated mosfet drivers and bootstrap diode internal soft-start and soft-stop power good monitoring 70% under- voltage protection 125% over- voltage protection - using low-side mosfet ? s r ds(on) over- temperature protection tdfn-10 3mmx3mm package lead free and green devices available (rohs compliant) g e n e r a l d e s c r i p t i o n a p p l i c a t i o n s notebook low cost pc wide input dc/dc regulators the ap w7199 is a single-phase, constant-on-time, and synchronous p wm controller, which drives n-channel mosfe t s. an internal 0.5v temperature-compensated reference voltage with high accuracy is designed to meet the requirement of low output voltage applications. the ap w7199 steps down high voltage to generate low-volt- age chipset or ram supplies in notebook computers. the p wm controller operates fixed 300khz pseudo-con- stant frequency p wm with an adaptive constant-on-time control. the device provides excellent transient response and accurate dc voltage output in either pfm or p wm mode. in pulse frequency mode (pfm), the ap w7199 pro- vides very high efficiency over light to heavy loads with loading-modulated switching frequencies. the device works in ultrasonic mode with pfm at no load. the unique ultrasonic mode maintains the switching frequency above 20khz, which eliminates noise in audio applications. t he ap w7199 is equipped with accurate over-current, output under-voltage, and output over-voltage protections. a power-on-reset function monitors the voltage on vcc to prevent wrong operation during power-on. the ap w7199 has a 1.5ms digital soft-start to ramp up the output voltage to reduce the start-up current. a soft-stop function actively discharges the output capacitors with controlled reverse inductor current. the ap w7199 is available in tdfn3x3-10 package. s i m p l i f i e d a pp li c a t i o n c i r c u i t v out l out q 2 en/extref APW7199 v in 5v q 1 c out r ocset ugate phase lgate/ocset pok boot vcc http://
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n n o t e : a n pe c l e a d - f r ee p r odu c t s c on t a i n m o l d i ng c o m pound s / d i e a tt a c h m a t e r i a l s a nd 100 % m a tt e t i n p l a t e t e r m i n a t i on f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n pe c l e a d - f r ee p r odu c t s m ee t o r e x c eed t he l e a d - f r ee r equ i r e m en t s o f i p c / j e d e c j - s t d - 020 d f o r m s l c l a ss i f i c a t i on a t l e a d - f r ee pea k r e f l o w t e m p e r a t u r e . a n pe c d e f i ne s ? g r e en ? t o m e a n l e a d - f r ee ( r o h s c o m p li a n t ) a nd ha l og en f r ee ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n ho m o g e ne o u s m a t e r i a l a nd t o t a l o f b r a nd c l do e s no t e x c e e d 15 0 0 p p m b y w e i g h t ) . p i n c o n f i g u r a t i o n a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) symbol parameter rating unit v cc vcc supply voltage (vcc to gnd) - 0.3 ~ 7 v v boot - gnd boot supply voltage (boot to gnd ) - 0.3 ~ 32 v v boot boot supply voltage (boot to phase) - 0.3 ~ 7 v all other pins (fb, vou t , pok, and en/extref to gnd) - 0.3 ~ v cc +0 .3 v ug ate voltage (ugate to phase) <400ns pulse width >400ns pulse width - 5 ~ v boot +0.3 - 0.3 ~ v boot +0.3 v lg ate /ocset voltage (lg ate to gnd) <400ns pulse width >400ns pulse width - 5 ~ v cc +0.3 - 0.3 ~ v cc +0.3 v v phase phase voltage (phase to gnd) <400ns pulse width >400ns pulse width - 5 ~ 3 2 - 1 ~ 25 v t j maximum junction temperature 150 o c t stg storage temperature - 65 ~ 150 o c t sdr maximum lead soldering temperature, 10 seconds 260 o c = t he r m a l p a d ( c onne c t ed t o g nd p l a ne f o r be tt e r he a t d i ss i pa t i on ) tdfn3x3-10 (top view) phase 3 10 en/extref boot 1 ugate 2 lgate/ocset 5 9 pok 7 fb 8 vout gnd 4 6 vcc note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. exposure to absolute maximum rating conditions for extended periods may affect device reliability. handling code package code xxxxx - date code temp erature range assembly m a t erial package code q b : t dfn3x3-10 temperature range i : -40 to 85 o c handling code tr : tape & reel assembly m a teri al g : halogen and lead free device apw719 9 apw719 9 q b : apw 7199 xxxxx
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 3 t h e r m a l c h a r a c t e r i s t i c s symbol parameter ty pical value unit q ja thermal resistance - junction to ambient (note 2) tdfn3x3 - 10 55 c/w n ote 2: q ja is measured with the component mounted on a high effective the thermal conductivity test board in free air. the exposed pad of package is soldered directly on the pcb. r e c o mm e n d e d o p e r a t i n g c o n d i t i o n s ( n o t e 3 ) symbol parameter range unit v in converter input voltage 3 ~ 25 v v cc vcc supply voltage 4.5 ~ 5.5 v v out converter output voltage 0.5 ~ 3.3 v i out converter output current 0 ~ 25 a t a ambient t emperature - 40 ~ 85 o c t j junction t emperature - 40 ~ 125 o c note 3 : refer to the typical application circuit. e l e c t r i c a l c h a r a c t e r i s t i c s refer to the typical application circuits. these specifications apply over v cc = 5 v , and t a = -40 ~ 85 c, unless otherwise specified. typical values are at t a = 25 c. APW7199 symbol parameter test condition s min. ty p. max. unit supp ly current i vcc - pwm vcc input bias current ugate and lgate open - 400 500 m a i vcc - pfm vcc input bias current ugate and lgate open - 350 450 m a i vcc_shdn vcc shutdown current v en/ext ref = 0v - - 7 m a reference v oltage v ref reference voltage - 0.5 - v regulation accuracy t a = - 40 o c ~ 85 o c, i out = 0 ~ 20a - 0.6 - +0.6 % line and load regulation 0a < i out < 20 a; 4 v < v cc < 5.5 v - 0.2 - +0.2 % i fb fb input bias current v fb = 0.5v - 0 .5 - 0.5 m a pwm controller t on (min) minimum on t ime of ugate over - temperature and v cc - 100 - ns t off (min) minimum o ff t ime of ugate over - temperature and v cc - 300 - ns t ss internal s oft - s tart t ime 1 1.5 2 ms vout pin input impedance - 130 - k w v out discharge resistance - 20 32 w zero crossing voltage threshold - 3 0 +3 mv pwm to pfm debounce time - 20 - m s pfm to pwm debounce time - 20 - m s
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) refer to the typical application circuits. these specifications apply over v cc = 5 v , and t a = -40 ~ 85 c, unless otherwise specified. typical values are at t a = 25 c. ap w7199 symbol parameter test condition s min. ty p. max. unit gate driver ug ate source resistance v boot = 5 v , v boot - v ugate = 0.5v - 1.5 3 w ug ate sink resistance v boot = 5 v , v ugate - v phase = 0.5v - 1 2 w l g ate source resistance v cc = 5 v , v cc - v l gate = 0.5v - 1.5 3 w l g ate sink resistance v cc = 5 v , v lgate - v gnd = 0.5v - 0.8 1.5 w dead t ime (note 4) 20 25 40 ns bootstrap diode v f forward voltage v cc - v boot - gnd , i f = 5ma - 0.8 1 v i r reverse leakage v boot - gnd = 30 v , v phase = 25 v, v cc = 5v - - 0.5 m a vcc power - on - reset ( por ) threshold v vcc_thr rising vcc por threshold voltage 4.05 4.2 4.35 v vcc por hysteresis 0.1 0.2 0.3 v oscill ator f sw switching frequency in pwm mode dc output current, v cc = 4.5v ~ 5.5v 270 300 330 khz minim um ultrasonic operating frequency v cc = 4.5v ~ 5.5v 20 25 - khz control inputs pwm converter shutdown threshold v en /extref falling - - 0.4 v external reference voltage input range v ref = v en/extref 0.5 - 2.5 v internal reference enable threshold v r ef = 0.5v (typical) , v en/extref rising 2.75 - - v en /extref l eakage current v en /extref = 0v - 0.1 - 0.1 m a maximum voltage slew rate of v ref external reference voltage used, v ref = v en/extref 8 - - mv / m s power ok indic ator (pok) v fb is from low to target value (pok goes high) 91 95 99 % ~3 m s noise filter, v fb falling (pok goes low) 65 70 75 % v pok pok threshold ~3 m s noise filter, v fb rising (pok goes low) 120 125 130 % i pok p ok leakage current v pok = 5v - 0.1 1.0 m a v pok pok output low voltage i pok = - 4ma - 0.5 1 v protection s i ocset i ocset source current i ocset sourc ing 9 10 11 m a v ocp_max built - in maximum ocp voltage 230 250 270 mv
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 5 APW7199 symbol parameter test condition s min. ty p. max. unit protection s (con t .) v uv u nder - v oltage p rotection threshold 65 70 75 % u nder - v oltage p rotection debounce interval - 2 - m s v ovr o ver - v oltage p rotection rising threshold 120 125 133 % o ver - v oltage p rotection fallin g threshold 100 105 110 % o ver - v oltage p rotection debounce interval - 2 - m s t otr o ver - t emperature p rotection rising threshold (note 4) - 150 - o c o ver - t emperature p rotection hyste r esis (note 4) - 20 - o c e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) note4: guaranteed by design. refer to the typical application circuits. these specifications apply over v cc = 5 v , and t a = -40 ~ 85 c, unless otherwise specified. typical values are at t a = 25 c.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s c on v e r t e r o u t pu t v o l t age , v o u t ( v ) converter input voltage, v in (v) converter output voltage vs. converter input voltage v cc =5v, v out =1.05v, i load =0a 1.058 1.056 1.054 1.040 1.060 1.052 1.050 1.048 1.046 1.044 1.042 5 10 15 20 0 25 s w i t c h i ng f r e quen c y , f s w ( k h z ) converter input voltage, v in (v) switching frequency vs. converter input voltage i out =4a pwm mode 5 7 9 11 13 15 17 19 21 23 25 3 270 330 320 310 300 290 280 s w i t c h i ng f r eq uen cy , f s w ( k h z ) switching frequency vs. converter output current converter output current, i out (a) v in =19v, v out =1.05v 0.01 0.10 1.00 10.00 100.00 0 350 300 250 200 150 100 50 converter output current, i out (a) e ff i c i en cy ( %) efficiency vs. load current , v out =1.05v v in =8v v in =19v h-side:apm4826 x1 l-side:apm4828 x1 0 10 70 80 90 60 50 100 40 30 20 0.10 1.00 10.00 0.01 100.00 r e f e r en c e v o l t a ge a c c u r a cy , v r e f ( v ) reference voltage accuracy vs. junction temperature junction temperature, t j ( o c ) -50 -30 10 50 90 110 130 70 30 -10 0.494 0.506 0.504 0.502 0.500 0.498 0.496 o c se t s o u r c i n g c u rr e n t, i o c s e t ( m a ) ocset sourcing current vs. junction temperature junction temperature, t j ( o c ) 9.6 10.4 10.2 10 9.8 -50 -30 10 50 90 110 130 70 30 -10
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 7 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) converter output voltage vs. converter output current c on v e r t e r o u t pu t v o l t age , v o u t ( v ) converter output current, i out (a) v in =19v, v out =1.05v, pwm mode 0 20 15 5 10 1.058 1.056 1.054 1.040 1.060 1.052 1.050 1.048 1.046 1.044 1.042
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 8 o p e r a t i n g w a v e f o r m s r e f e r t o t h e t y p i c a l a p p li c a t i o n c i r c u i t . t he t e s t c ond i t i o n i s v i n = 1 9 v , t a = 2 5 o c un l e ss o t he r w i s e s pe c i f i e d . e n a b l e a t z e r o i n i t i a l v o l t a g e o f v o u t ch2: v out , 1v/div, dc ch3: v phase , 20v/div, dc time: 5ms/div ch1: v en/extref , 5v/div, dc ch4: v pok , 5v/div, dc 1 2 3 4 v en / ex tr ef v out v phase v pok e n a b l e b e f o r e e n d o f s o f t- s t o p s h u t d o w n a t i o u t = 2 0 a ch2: v out , 1v/div, dc ch3: v phase , 20v/div, dc time: 10 m s/div ch1: v en/extref , 5v/div, dc ch4: v pok , 5v/div, dc s h u t d o w n w i t h s o f t - s t o p a t n o lo a d ch2: v out , 1v/div, dc ch3: v phase , 20v/div, dc time: 20ms/div ch1: v en/extref , 5v/div, dc ch4: v pok , 5v/div, dc 1 4 2 3 v en / ex tr ef v out v phase v pok 1 4 2 3 v en / ex tr ef v out v phase v pok 1 2 3 4 v en / ex tref v out v phase v pok ch2: v out , 1v/div, dc ch3: v phase , 20v/div, dc time: 1ms/div ch1: v en/extref , 5v/div, dc ch4: v pok , 5v/div, dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 9 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p li c a t i o n c i r c u i t . t he t e s t c ond i t i o n i s v i n = 1 9 v , t a = 2 5 o c un l e ss o t he r w i s e s pe c i f i e d . l o a d t r a n s i e n t 0 a - > 10 a lo a d t r a n s i e n t 10 a - > 0 a c u rr e n t- l i m i t a n d u v p r o t e c t i o n s ch2: v lgate , 5v/div, dc ch3: v out , 1v/div, dc time: 20 m s/div ch1: v phase , 20v/div, dc ch4: i l , 10a/div, dc 1 4 2 3 v phase v lgate v out i l s h o r t c i r c u i t t e s t ch2: v lgate , 5v/div, dc ch3: v out , 1v/div, dc time: 20 m s/div ch1: v phase , 20v/div, dc ch4: i l , 10a/div, dc 1 4 2 3 v phase v lgate v out i l 1 4 3 2 v phase v lgate v out i out ch2: v lgate , 5v/div, dc ch3: v out , 50mv/div, ac time: 10 m s/div ch1: v phase , 20v/div, dc ch4: i out , 10a/div, dc 1 4 2 3 v phase v lg a te v out i out ch2: v lgate , 5v/div, dc ch3: v out , 50mv/div, ac time: 10 m s/div ch1: v phase , 20v/div, dc ch4: i out , 10a/div, dc
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 1 0 o p e r a t i n g w a v e f o r m s ( c o n t . ) r e f e r t o t h e t y p i c a l a p p li c a t i o n c i r c u i t . t he t e s t c ond i t i o n i s v i n = 1 9 v , t a = 2 5 o c un l e ss o t he r w i s e s pe c i f i e d . o p e r a t i n g a t u l t r a s o n i c m o d e o p e r a t i n g a t p f m m od e 1 4 3 2 v phase v lg a te v out i l ch2: v lgate , 5v/div, dc ch3: v out , 50mv/div, ac time: 10 m s/div ch1: v phase , 10v/div, dc ch4: i l , 5a/div, dc ch2: v lgate , 5v/div, dc ch3: v out , 50mv/div, ac time: 2 m s/div ch1: v phase , 10v/div, dc ch4: i l , 5a/div, dc 1 4 2 3 v phase v lgate v out i l o p e r a t i ng a t p w m m o d e ch2: v lgate , 5v/div, dc ch3: v out , 50mv/div, ac time: 2 m s/div ch1: v phase , 10v/div, dc ch4: i l , 5a/div, dc 1 4 3 2 v phase v lgate v out i l
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 1 1 p i n d e s c r i p t i o n pin no. name function 1 boot this p in provides ground referenced bias voltage to the high - side mosfet driver. a bootstrap circuit with a diode connected to 5 v is used to create a voltage suitable to drive a logic - level n - channel mosfet. 2 ug ate connect this pin to the high - side n - channel mosfet ?s gate. this pin provides gate drive for the high - side mosfet. 3 phase the pin provides return path for the high - side mosfet driver ? s pull - low current. connect this pin to the high - side mosfet ? s source. 4 gnd t he gnd terminal provides return path for the ic ? s bias current and the low - side mosfet driver ? s pull - low current. connect the pin to the system ground via very low impedance layout on pcbs. 5 lg ate/ocset low - side gate driver output and over - current settin g input. this pin is the gate driver for low - side mosfe t. 6 vcc connect this pin to a 5 v supply voltage. this pin provides bias supply for the control circuitry and the low - side mosfet driver. the voltage at this pin is monitored for the power - on - reset (p or) purpose. decoupling capacitor (4.7 m f) be connected to gnd for noise decoupling. 7 fb output v oltage f eedback p in. this pin is connected to the resistive divider that set the desired output voltage. the p ok , uv p , and ovp circuits detect this signal to report output voltage status. 8 vout the vout pin makes a direct measurement of the converter output voltage. the vout pin should be connected to the top feedback resistor at the converter output. 9 pok p ok is an open drain output used to in dicate the st atus of the output voltage. connect the pok pin to +5v through a pull - high resisto r. 10 en/extref enable /shutdown pin or external reference selection of the pwm controlle r .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 1 2 b l o c k d i a g r a m fb error comparator ov uv 70% v ref 125% v ref v ref por vcc en/ extref digital soft - start p w m s i gna l c on t r o ll e r v cc boot ugate phase l gate / ocset thermal shutdown gnd pok vout fault latch logic on-time generator v ref x 95% /70% v ref x 125% z c phase ocp debounce time v cc sample and hold v rocset to lgate /ocset 10 m a v rocset sense low-side v out v out
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 1 3 t y p i c a l a p p l i c a t i o n c i r c u i t en/extref pok vcc gnd ugate boot phase lgate/ocset vout fb r pok r vcc c vcc c out r top r gnd q 1 q2 l out c boot APW7199 c in v pok v in v out =1.05v 100k 2.2 4.7 m f 11k, 1% 10k, 1% c fb-vout 10nf 150 m f x 2 1.5 m f 3v ~ 25v 10 m f x 2 0.1 m f apm4826 apm4828 r ocset 3.24k, 1% 5v schottky diode
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 www . a n p e c . c o m . t w 1 4 f un c t i o n d e s c r i p t i o n constant-on-time pwm controller with input feed-for- ward pulse-frequency modulation (pfm) ultrasonic mode the constant-on-time control architecture is a pseudo- fixed frequency with input voltage feed-forward. this ar- chitecture relies on the output filter capacitor ? s effective series resistance (esr) to act as a current-sense resis- tor so the output ripple voltage provides the p wm ramp signal. in pfm operation, the high-side switch on-time controlled by the on-time generator is determined solely by a one-shot whose pulse width is inversely propor- tional to the input voltage and directly proportional to the output voltage. in p wm operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block. the switching frequency control circuit senses the switch- ing frequency of the high-side switch and keeps regulat- ing it at a constant frequency in pwm mode. the design improves the frequency variation and is more outstand- ing than a conventional constant-on-time controller, which has large switching frequency variation over input voltage, output current, and temperature. both in pfm and p wm, the on-time generator, which senses input voltage on phase pin, provides very fast on-time response to input line transients. another one-shot sets a minimum off-time (typical: 300ns). the on-time one-shot is triggered if the error com- parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- shot has timed out. in pfm mode, an automatic switchover to pulse-frequency modulation (pfm) takes place at light loads. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. this mechanism causes the threshold between pfm and p wm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). the on-time of pfm is given by: where f sw is the nominal switching frequency of the con- verter in p wm mode. the load current at handoff from pfm to p wm mode is given by: in this case, ap w7199 operates in ultrasonic mode with pfm when the load is zero. the ultrasonic mode is illus- trated as below description. the ultrasonic mode activates an unique pfm mode with a minimum switching frequency of 20khz. the minimum frequency 20khz of ultrasonic mode eliminates audio- frequency interference in light load condition. it will transit to unique pfm mode when output loading makes the frequency bigger than ultrasonic frequency. in ultrasonic mode, the controller automatically transits to fixed-frequency p wm operation when the load reaches the same critical conduction point (i load(pfm to pwm) ). when the controller detects that no switching has oc- curred within about 40 m s ( typical), an ultrasonic pulse will be occurred. the ultrasonic controller turns on the low-side mosfet firstly to reduce the output voltage. af- ter feedback voltage drops below the internal reference voltage, the controller turns off the low-side mosfet and triggers a constant-on-time. when the constant-on-time has expired, the controller turns on the low-side mosfet again until the inductor current is below the zero-cross- ing threshold. the behavior is the same as pfm mode. in out sw pfm on v v f 1 t = - in out sw out in pfm on out in ) pfmtopwm ( load v v f 1 l v v t l v v 2 1 i - = - = - power-on-reset (por) a power-on-reset (por) function is designed to prevent wrong logic controls when the vcc voltage is low. the por function continually monitors the bias supply volt- age on the vcc pin if at least one of the enable pins is set high. when the rising vcc voltage reaches the rising por voltage threshold (4.2v, typical), the por signal goes high and the chip initiates soft-start operations. when this voltage drops lower than 4.0v (typical), the por dis- ables the chip.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 www . a n p e c . c o m . t w 1 5 f u n c t i o n d e s c r i p t i o n ( c o n t . ) en/extref pin control digital soft-start power ok indicator the voltage (v en/extref ) applied to en/extref pin se- lects either enable-shutdown or adjustable external reference. when v en/extref is above the en high thresh- old (2.75v, typical), the p wm is enabled. when v en/extref is from 0.5v to 2.5v, the output voltage can be programmed as same as v en/extref voltage. when v en/extref is below the en low threshold (0.4v, typical), the chip is in the shutdown and only low leakage current is taken from vcc. the slew rate of v en/extref must be faster than 0.5v/ m s to avoid wrong output voltage. the ap w7199 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. the slew rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- start process. the figure 1 shows soft-start sequence. when the en/extref pin is pulled above the rising en threshold voltage, the v ocset voltage is equal to 10 m a x r ocset . when vcc rising por threshold is triggered, the device starts to sample and hold the current-limit setting threshold. the sample time is as below: [i ocset ( m a) x r ocset (k w ) x 4.0 + 70] m s. during soft-start stage before the pok pin is ready, the under-voltage protection is prohibited. the over-voltage and over-current protection functions are enabled. if the output capacitor has residue voltage before start-up, both low-side and high-side mosfe t s are in off-state until the internal digital soft-start voltage is equal to the v fb voltage. this will ensure that the output voltage starts from its existing voltage level. in the event of under-voltage or shutdown, the chip en- ables the soft-stop function. the soft-stop function dis- charges the output voltages to the gnd through an inter- nal 20 w switch. cycling the en/extref enable signal or vcc power-on-reset signal can reset the latch. figure 1. soft-start sequence the ap w7199 features an open-drain pok pin to indi- cate output regulation status. in normal operation, when the output voltage rises 95% of its target value, the pok goes high. when the output voltage outruns 70% or 125% of the target voltage, pok signal will be pulled low immediately. since the fb pin is used for both feedback and monitor- ing purposes, the output voltage deviation can be coupled directly to the fb pin by the capacitor in parallel with the voltage divider as shown in the typical applications. in order to prevent false pok from dropping, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient and the pok comparator has a built-in 3 m s noise filter. f r o m t ss = t 2 -t 1 = 1.5ms en v out v cc v pok t 1 t 2 95% x v ref v t t 0 w hen c u rr en t - li m i t s e tt i ng a c t i on ha s f i n i s he d , t he d e v i c e i n i t i a t e s a s o f t - s t a r t p r o c e s s t o r a m p up t he o u t pu t v o l t ag e . t he s o ft - s t a r t i n t e r v a l , t ss , i s abou t 1 . 5 m s ( t y p i c a l v a l ue ) . under- voltage protection (uvp) in the operational process, if a short-circuit occurs, the output voltage will drop quickly. when load current is big- ger than current-limit threshold value, the output voltage will fall out of the required regulation range. the under- voltage protection circuit continually monitors the v fb af- ter soft-start is completed. if a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the device starts to soft-stop process to shut down the output gradually. the under-voltage threshold is 70% of the normal output voltage. the under-voltage comparator has a built-in 2 m s noise filter to prevent the chip from wrong uvp shutdown caused by noise. cy- cling the en/extref enable signal or vcc power-on- reset signal can reset the latch.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 www . a n p e c . c o m . t w 1 6 f u n c t i o n d e s c r i p t i o n ( c o n t . ) over- voltage protection (ovp) the over-voltage function monitors the output voltage by the fb pin. when the fb voltage increases over 125% of the reference voltage due to the high-side mosfet fail- ure or for other reasons, the over-voltage protection com- parator designed with a 2 m s noise filter will force the low- side mosfet gate driver fully turn on. this action actively pulls down the output voltage. when the fb voltage de- creases below 105%, the ovp comparator is disengaged and both high-side and low-side drivers turn off. this ovp scheme only clamps the voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output from low-side mosfet driver. it ? s a common problem for ovp schemes with a latch. once an over-voltage fault condition is set, it can only be reset by toggling en/extref or vcc power- on-reset signal. over- temperature protection (otp) when the junction temperature increases above the ris- ing threshold temperature totr, the ic will enter the over-temperature protection state that suspends the pwm, which forces the ug ate and lg ate gate drivers output low. the thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 20 o c. the otp is designed with a 20 o c hysteresis to lower the av- erage t j during continuous thermal overload conditions, which increases lifetime of the ap w7199. c u r r e n t - l i m i t t h e c u rr en t - li m i t c i r c u i t e m p l o ys a ? v a l l e y ? c u r r e n t - s en s - i n g a l g o r i t h m ( s e e f i g u r e 2 ) . t h e a p w 7 1 9 9 u s e s t h e l o w - s i de m o s f e t r d s ( o n ) o f t he syn c h r ono u s r e c t i f i e r a s a c u rr en t - s en s i ng e l e m en t. if t he m agn i t ude o f t he c u rr en t - s e n s e s i g n a l a t p h a s e p i n i s a b o v e t h e c u r r e n t - l i m i t t h r e s ho l d , t he p w m i s no t a ll o w ed t o i n i t i a t e a ne w c y c l e . t h e a c t u a l p ea k c u r r e n t i s g r ea t e r t h a n t h e c u rr e n t - l i m i t t h r e s h o l d b y a n a m ou n t e q ua l t o t he i n d u c t o r r i pp l e c u r r e n t . t he r e f o r e , t he e x a c t c u rr en t - li m i t c ha r a c t e r i s t i c a nd m a x i - m u m l o a d c a p a b i l i t y a r e t h e f u n c t i o n s o f t h e s e n s e r e s i s t a n c e , i nd u c t o r v a l ue , a nd i n p u t v o l t a ge . figure 2. current-limit algorithm a resistor (r ocset ), connected from the lg ate/ocset to gnd, programs the current-limit threshold. before the ic initiates a soft-start process, an internal current source, i ocset (10 m a typical), flowing through the r ocset develops a voltage (v ocset ) across the r ocset . the device holds v ocset and stops the current source, i ocset , during normal operation. the relationship between the sampled volt- age v ocset and the current-limit threshold i limit is given by: 10 m a x r ocset = i limit x r ds(on) i limit can be expressed as i out minus half of peak-to-peak inductor current. the APW7199 has an internal current-limit voltage (v ocset_max ), and the value is 0.25v typical. when the r ocset x i ocset exceeds 0.25v or the r ocset is floating or not connected, the over current threshold will be the internal default value 0.25v. the pcb layout guidelines should ensure that noise and dc errors do not corrupt the current-sense signals at phase. place the hottest power mosef t s as close to the ic as possible for best thermal coupling. when com- bined with the under-voltage protection circuit, this cur- rent-limit method is effective in almost every circumstance. time i n du c t o r c urr e n t 0 i peak i out i limit g i
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 www . a n p e c . c o m . t w 1 7 a pp l i c a t i o n i n f o r m a t i o n where 0.5 is the reference voltage, r top is the resistor connected from converter ? s output to fb, and r gnd is the resistor connected from fb to gnd. suggested r gnd is in the range from 1k to 20k w . to prevent stray pickup, lo- cate resistors r top and r gnd close to APW7199. similarl y, when v en/extref is from 0.5v to 2.5v, the output voltage can be programmed as same as v en/extref voltage. o u t p u t i nd u c t o r s e l e c t i o n t h e d u t y cy c l e ( d ) o f a b u c k c o n v e r t e r i s t h e f u n c t i o n o f t h e i n pu t v o l t age a nd ou t pu t v o l t age . o n c e a n ou t pu t v o l t age i s f i x ed , i t c a n be w r i tt en a s : in out v v d = in out sw out in ripple v v l f v - v i = o u t pu t c a p a c i t o r s e l e c t i o n the inductor value (l) determines the inductor ripple current, i ripple , and affects the load transient response. higher inductor value reduces the inductor ? s ripple cur- rent and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: esr ripple esr sw out ripple out c r i v f 8c i v = d = d w h e r e f s w i s t h e s w i t c h i n g f r e q u e n c y o f t h e r e g u l a t o r . a l t ho ugh t he i ndu c t o r v a l ue a nd f r equen cy a r e i n c r e a s ed a nd t h e r i pp l e c u r r en t a nd v o l t age a r e r edu c ed , a t r a deo f f e x i s t s be t w een t he i ndu c t o r ? s r i pp l e c u rr en t a nd t he r egu - l a t o r l o a d t r a n s i e n t r e s p on s e t i m e . a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. increasing the switching frequency (f sw ) also reduces the ripple current and voltage, but it will increase the switching loss of the mosfe t s and the power dissipa- tion of the converter. the maximum ripple current occurs at the maximum input voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. in some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. this results in a larger output ripple voltage. besides, the inductor needs to have low dcr to reduce the loss of efficiency. output voltage ripple, the transient voltage deviation and the stability issue are factors which have to be taken into consideration when selecting an output capacitor. higher capacitor value and lower esr reduce the output ripple and the load transient drop. generally, selecting high per- formance low esr capacitors is recommended for switching regulator applications. in addition to high fre- quency noise related to mosfet turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop d v cout and esr voltage drop d v esr caused by the ac peak-to-peak inductor ? s current. these two voltages can be represented by: these two components constitute a large portion of the total output voltage ripple. in some applications, multiple capacitors have to be paralleled to achieve the desired esr value. if the output of the converter has to support another load with high pulsating current, more capaci- tors are needed in order to reduce the equivalent esr and suppress the voltage ripple to a tolerable level. nevertheless, the constant-on-time (cot) control archi- tecture relies on the output capacitor ? s esr to act as a current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. for stability issue, the output ripple also need to be considered. by stability experi- ment result, we suggest the feedback ripple is above 25mv when operated in the internal mode and above 40mv when operated in the external mode. t o support a load transient that is faster than the switch- ing frequency, more capacitors are needed for reducing ? ? ? ? ? + = gnd top out r r 1 0.5 v o u t p u t v o l t a g e s e t t i n g the output voltage is adjustable from 0.5v to 3.3v with a resistor-divider connected with fb, gnd, and converter ?s output. the voltage (v en/extref ) applied to en/extref pin selects adjustable external reference from 0.5v to 2.5v. using 1% or better resistors for the resistor-divider is recommended. the output voltage is determined by:
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 www . a n p e c . c o m . t w 1 8 a pp l i c a t i o n i n f o r m a t i o n ( c o n t . ) o u t p u t c a p a c i t o r s e l e c t i o n ( c o n t . ) i n p u t c a p a c i t o r s e l e c t i on t he i n pu t c a pa c i t o r i s c ho s e n ba s ed on t he v o l t age r a t i ng a n d t he r m s c u r r en t r a t i n g . f o r r e li a b l e ope r a t i on , s e l e c t - i n g t h e c a p a c i t o r v o l t a g e r a t i n g t o b e a t l ea s t 1 . 3 t i m e s h i g h e r t h a n t h e m a x i m u m i np u t v o l t a g e . t h e m a x i m u m r m s c u r r e n t r a t i n g r e q u i r e m e n t i s a p p r o x i m a t e l y i o u t / 2 , w he r e i o u t i s t he l oa d c u rr en t . d u r i ng po w e r- u p , t he i n pu t c a pa c i t o r s ha v e t o ha n d l e g r e a t a m oun t o f s u r g e c u rr en t. f o r l o w - du t y no t eb oo k a pp l i a c t i on s , c e r a m i c c a pa c i t o r i s r e c o m m e n d e d . t h e c a p a c i t o r s m u s t b e c o n n e c t e d b e - t w ee n t h e d r a i n o f h i g h - s i d e m o s f e t a nd t he s ou r c e o f l o w - s i de m o s f e t w i t h v e r y l o w - i m pe a d a n c e p c b l a y ou t. m o s f e t s e l e c t i o n t h e s e l e c t i o n o f t h e n - c h an n e l p o w e r m o s f e t s a r e d e t e r m i n e d b y t h e r ds(on) , r e v e r s i n g t r an s f e r c ap a c i - t an c e ( c r ss ) a n d m a x i m u m o u t p u t c u r r e n t r e q u i r e m e n t . t h e l o s s e s i n t h e m o s f e t s h a v e t w o c o m p o n e n t s : c o n d u c t i o n l o s s a n d t r an s i t i o n l o s s . f o r t h e h i g h - s i d e a n d l o w - s i d e m o s f e t s , t h e l o s s e s a r e a p p r o x i m a t e l y g i v e n b y t he f o ll o w i n g e qu a t i on s : p high-side = i out 2 (1+ tc)(r ds(on) )d + (0.5)( i out )(v in )( t sw )f s w p low-side = i out 2 (1+ tc)(r ds(on) )(1-d) l a y ou t c o n s i d e r a t i o n during turn-off, current stops flowing in the mosfet and is freewheeling by the low side mosfet and parasitic diode. any parasitic inductance of the circuit generates a large voltage spike during the switching interval. in general, using short and wide printed circuit traces should minimize interconnecting impedances and the magni- tude of voltage spike. besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. fig- ure 3 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. com- ponents along the bold lines should be placed lose together. below is a checklist for your layout: where i out is the load current tc is the temperature dependency of r ds(on) f sw is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfe t s have conduction losses while the high-side mosfet includes an additional transition loss. the switching interval, t sw , is the function of the re- verse transfer capacitance c rss . the (1+tc) term is a factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs. t emperature ? curve of the power mosfet. = k e ep t h e s w i t c h i n g n o d e s ( u g a t e , l g a t e / o c se t , b o o t , an d p h a s e ) a w a y f r o m s e n s i t i v e s m a l l s i g n a l n o d e s s i n c e t h e s e n o d e s a r e f a s t m o v i n g s i g na l s . t h e r e f o r e , k e e p t r a c e s t o t h e s e n o d e s a s s h o r t a s p o s - s i b l e a nd t h e r e s h ou l d be n o o t he r w e a k s i gna l t r a c e s i n pa r a ll e l w i t h t h e s e s t r a c e s o n a n y l a y e r . = t h e s i g n a l s g o i n g t h r o u g h t h e s e s t r a c e s h a v e b o t h h i gh d v / d t a nd h i gh d i / d t w i t h h i gh pe a k c h a r g i ng a nd d i s - c h a r g i n g c u rr e n t . t he t r a c e s f r o m t h e ga t e d r i v e r s t o t he m o s f e t s ( u g a t e a n d l g a t e / o c se t ) s hou l d be s ho r t a nd w i de . = p l a c e t h e s o u r c e o f t h e h i g h - s i d e m o s f e t a n d t h e d r a i n o f t he l o w - s i de m o s f e t a s c l o s e a s po ss i b l e . m i n i - m i z i n g t h e i m p e d a n c e w i t h w i d e l a y o u t p l a n e b e t w e e n t he t w o pad s r edu c e s t he v o l t ag e boun c e o f t he node . i n a d d i t i on , t h e l a r g e l a y o u t p l a ne b e t w e en t he d r a i n o f t h e m o s f e t s ( v i n a n d p h a s e n o d e s ) c a n g e t b e t t e r h ea t s i n k i n g . in any high switching frequency converter, a correct lay- out is important to ensure proper operation of the regulator. with power devices switching at higher frequency, the resulting current transient will cause volt- age spike across the interconnecting impedance and parasitic circuit elements. as an example, consider the turn-off transition of the p wm mosfet. before turn-off condition, the mosfet is carrying the full load current. = d e c ou p l i n g c a pa c i t o r s , t he r e s i s t o r - d i v i d e r , a n d bo o t c a p a c i t o r s h ou l d b e c l o s e t o t h e i r p i n s . ( f o r e x a m p l e , p l a c e t he de c o up li ng c e r a m i c c a pa c i t o r c l o s e t o t he d r a i n o f t he h i g h - s i d e m o s f e t a s c l o s e a s p o s s i b l e . ) the voltage excursion during load step change. another aspect of the capacitor selection is that the total ac cur- rent going through the capacitors has to be less than the rated rms current specified on the capacitors in order to prevent the capacitor from over-heating.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 1 9 = locate the resistor-divider close to the fb pin to mini- mize the high impedance trace. in addition, fb pin traces can ? t be close to the switching signal traces (ug ate, lg ate/ocse t , boo t , and phase). = t h e i n p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e d r a i n o f t h e h i g h - s i d e m o s f e t , a n d t h e o u t p u t b u l k c a p a c i t o r s s h o u l d b e c l o s e t o t h e l o a d s . t h e i n p u t c a p a c i t o r ? s g r o u n d s h o u l d b e c l o s e t o t h e g r o u n d s o f t h e o u t p u t c a p a c i t o r s a n d l o w - s i d e m o s f e t . l a y o u t c o n s i d e r a t i o n ( c o n t . ) = the r ocset resistance should be placed near the ic as close as possible. figure 3. a pp l i c a t i o n i n f o r m a t i o n ( c o n t . ) close to ic vcc boot phase ugate lgate/ocset v in v out l o a d APW7199 r ocset
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 2 0 p a c k a g e i n f o r m a t i o n t d f n 3 x 3 - 1 0 0.70 0.069 0.028 0.002 0.50 bsc 0.020 bsc 0.20 0.008 k 2.90 3.10 0.114 0.122 2.90 3.10 0.114 0.122 s y m b o l min. max. 0.80 0.00 0.18 0.30 2.20 2.70 0.05 1.40 a a1 b d d2 e e2 e l millimeters a3 0.20 ref tdfn3x3-10 0.30 0.50 1.75 0.008 ref min. max. inches 0.031 0.000 0.007 0.012 0.087 0.106 0.055 0.012 0.020 note : 1. followed from jedec mo-229 veed-5. pin 1 corner e l k e 2 d2 a1 a3 b a e pin 1 d
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 2 1 c a r r i e r t a p e & r e e l d i m e n s i o n s a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 h t1 a d application a h t1 c d d w e1 f 178.0 ? 2.00 50 min. 8.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 8.0 ? 0.20 1.75 ? 0.10 3.5 ? 0.05 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tdfn3x3 - 10 4.0 ? 0.10 4.0 ? 0.10 2.0 ? 0.05 1.5+0.10 - 0.00 1.5 min. 0.6+0.00 - 0 .40 3.35 ? 0.20 3.35 ? 0.20 1.30 ? 0.20 (mm) d e v i c e s p e r u n i t package ty pe unit quantity tdfn3x3 - 10 tape & reel 3000
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 2 2 t a p i n g d i r e c t i o n i n f o r m a t i o n tdfn3x3-10 c l a s s i f i c a t i o n p r o f i l e user direction of feed
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 2 3 c l a ss i f i c a t i o n r e f l o w p r o f i l e s ( c o n t . ) table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ t j =125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a1 15 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma r e li a b i l i t y t e s t p r o g r a m profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 3 - a u g . , 2 0 1 0 a p w 7 1 9 9 w w w . a n p e c . c o m . t w 2 4 c u s t o m e r s e r v i c e a np ec e l e c t r on i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , la ne 218 , s e c 2 j hon g s i n g r d ., s i nd i a n c i t y , t a i pe i c oun t y 23 146 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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